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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9RS08LA8 Rev. 1, 10/2008
MC9RS08LA8
48 QFN Case 1314 7 mm2
TBD
48 LQFP Case 932 7 mm2
MC9RS08LA8
Features: * 8-Bit RS08 Central Processor Unit (CPU) - Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature range of -40C to 85C - Subset of HC08 instruction set with added BGND instruction * On-Chip Memory - 8 KB flash read/program/erase over full operating voltage and temperature - 256-byte random-access memory (RAM) - Security circuitry to prevent unauthorized access to flash contents * Power-Saving Modes - Wait and stop * Clock Source Options - Oscillator (XOSC) -- Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 1 MHz to 16 MHz - Internal clock source (ICS) -- Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; supports bus frequencies up to 10 MHz * System Protection - Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock - Low-voltage detection with reset or interrupt; selectable trip points - Illegal opcode detection with reset - Illegal address detection with reset - Flash block protection * Development Support - Single-wire background debug interface - Breakpoint capability to allow single breakpoint setting during in-circuit debugging * Peripherals - LCD -- Up to 8 x 21 or 4 x 25 segments; compatible with 5 V or 3 V LCD glass displays using on-chip charge pump; functional in wait, stop modes for very low power LCD operation; frontplane and backplane pins multiplexed with GPIO functions; selectable frontplane and backplane configurations - ADC -- 6-channel, 10-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop; fully functional from 2.7 V to 5.5 V. - TPM -- One 2-channel 16-bit timer/pulse-width modulator (TPM) module - SCI -- One 2-channel serial communications interface module with optional 13-bit break; LIN extensions - SPI -- One serial peripheral interface module in 8-bit data length mode with a receive data buffer hardware match function - ACMP -- Analog comparator with option to compare to internal reference - MTIM -- One 8-bit modulo timer - KBI -- 8-pin keyboard interrupt module - RTI -- One real-time interrupt module with optional reference clock. * Input/Output - 33 GPIOs including 1 output only pin and 1 input only pin. - Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins. * Package Options - 48-pin QFN - 48-pin LQFP
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .7 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .9 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .14 3.7 External (XOSC) and Internal (ICS) Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.8.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . . 3.9 Analog Comparator (ACMP) Electrical . . . . . . . . . . . . 3.10 Internal Clock Source Characteristics . . . . . . . . . . . . . 3.11 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 19 19 20 22 22 23 25 26
4 5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document.
Revision 1 Date 10/9/2008 Initial public released. Description of Changes
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9RS08LA8RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 2 Freescale Semiconductor
MCU Block Diagram
1
VREFH VREFL VDDAD VSSAD
MCU Block Diagram
6-CH 10-BIT ANALOG-TO-DIGITAL CONVERTER(ADC) 4-BIT KEYBORAD RS08 CORE INTERRUPT(KBI) SERIAL PERIPHERAL INTERFACE (SPI) ANALOG COMPARATOR (ACMP) RS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP WAKEUP VPP RTI 2-CH TIMER/PWM LVD MODULE (TPM) RESET XTAL EXTAL SS SPSCK MISO MOSI ACMP+ ACMP- ACMPO PTA0/SS/KBIP0/ADP0/LCD27 PTA1/SPSCK/KBIP1/ADP1/LCD26 KBIP[0:7]
The block diagram, Figure 1, shows the structure of the MC9RS08LA8 MCU.
ADP[5:0]
PORT A
PTA2/MISO/KBIP2/ADP2/RxD/LCD25 PTA3/MOSI/KBIP3/ADP3/TxD/LCD24 PTA4/KBIP4/ADP4/LCD23 PTA5/KBIP5/ADP5/LCD22 PTA6/KBIP6/ACMP+ PTA7/KBIP7/ACMP-
CPU
BDC
PORT B
PTB0/EXTAL PTB1/XTAL PTB2/RESET/VPP PTC0/RxD
TPMCH0 TPMCH1 TCLK
PORT C
PTC1/TxD PTC2/TPMCH0 PTC3/TPMCH1 PTC6/ACMPO/BKGD/MS
USER FLASH 8192 BYTES USER RAM 256 BYTES 20 MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR TCLK SERIAL COMMUNICATION INTERFACE (SCI)
TxD RxD
PTC7/TCLK/LCD28 PTD0/LCD0 PTD1/LCD1
PORT D
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz (XOSC) VDD VSS VOLTAGE REGULATOR
8-bit Modulo Timer (MTIM)
PTD2/LCD2 PTD3/LCD3 PTD4/LCD4 PTD5/LCD5 PTD6/LCD6 PTD7/LCD7 PTE0/LCD8
LCD[0:7] VLL1 VLL2 VLL3 VCAP1 VCAP2 LCD28 LIQUID CRYSTAL DISPLAY DRIVER (LCD) LCD[16:21] LCD[22:27] LCD[8:15]
PTE1/LCD9
PORT E
PTE2/LCD10 PTE3/LCD11 PTE4/LCD12 PTE5/LCD13 PTE6/LCD14 PTE7/LCD15 LCD[16:21]
NOTES: 1. PTB2/RESET/VPP is an input only pin when used as port pin 2. PTC6/ACMPO/BKGD/MS is an output only pin
Figure 1. MC9RS08LA8 Series Block Diagram
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 3
Pin Assignments
2
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin Number 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PTB2 PTC0 PTC1 PTC2 PTC3 PTC6 PTC7 PTA0 PTA1 PTA2 SS SPSCK MISO ACMPO RESET RxD TxD TPMCH0 TPMCH1 BKGD TCLK KBIP0 KBIP1 KBIP2 ADP0 ADP1 RxD ADP2 MS LCD28 LCD27 LCD26 LCD25 PTB0 PTB1 PTA6 PTA7 KBIP6 KBIP7 ACMP+ ACMP- VSSAD/VREFL VDDAD/VREFH EXTAL XTAL VDD VSS VPP Port Pin PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Alt 1 <-- Lowest Priority Alt 2 --> Highest Alt 3 Alt 4 Alt 5 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3
This section shows the pin assignments in the packages available for the MC9RS08LA8 series.
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 4 Freescale Semiconductor
Pin Assignments
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number 48 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 Port Pin PTA3 PTA4 PTA5 Alt 1 MOSI <-- Lowest Priority Alt 2 KBIP3 KBIP4 KBIP5 TxD ADP4 ADP5 --> Highest Alt 3 Alt 4 ADP3 Alt 5 LCD24 LCD23 LCD22 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10 LCD9 LCD8
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 5
Pin Assignments
PTE2/LCD10
PTE3/LCD11
PTE4/LCD12
PTE5/LCD13
PTE6/LCD14
PTE7/LCD15
PTE0/LCD8
PTE1/LCD9
LCD16
LCD17
LCD18
48 47 46 45 44 43 42 41 40 39 38 37
PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2
LCD19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PTB0/EXTAL PTC0/RxD PTA7/KBIP7/ACMP- PTA6/KBIP6/ACMP+ PTB1/XTAL PTB2/RESET/VPP VSSAD/VREFL VDDAD/VREFH PTC1/TxD VLL3 VDD VSS
36 35 34 33 32 31 30 29 28 27 26 25
LCD20 LCD21 PTA5/KBIP5/ADP5/LCD22 PTA4/KBIP4/ADP4/LCD23 PTA3/MOSI/KBIP3/ADP3/TxD/LCD24 PTA2/MISO/KBIP2/ADP2/RxD/LCD25 PTA1/SPSCK/KBIP1/ADP1/LCD26 PTA0/SS/KBIP0/ADP0/LCD27 PTC7/TCLK/LCD28 PTC6/ACMPO/BKGD/MS PTC3/TPMCH1 PTC2/TPMCH0
Figure 2. MC9RS08LA8 Series in 48-Pin QFN/LQFP Package
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 6 Freescale Semiconductor
Electrical Characteristics
3
3.1
Electrical Characteristics
Parameter Classification
This chapter contains electrical and timing specifications.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
T
D
NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this chapter. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 3. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range Symbol VDD IDD VIn ID Tstg Value 2.7 to 5.5 120 -0.3 to VDD + 0.3 25 -55 to 150 Unit V mA V mA C
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 7
Electrical Characteristics
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP pin which is internally clamped to VSS only. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single layer board 48-pin LQFP 48-pin QFN JA Four layer board 48-pin LQFP 48-pin QFN 49 28 71 84 C/W TA TJMAX Symbol TL to TH -40 to 85 105 Value C C Unit
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD x JA) Eqn. 1
where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C /W PD = Pint + PI/O Pint = IDD x VDD, Watts chip internal power PI/O = Power dissipation on input and output pins user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 8 Freescale Semiconductor
Electrical Characteristics
(if PI/O is neglected) is:
PD = K / (TJ + 273C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD x (TA + 273C) + JAx (PD)2 Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation A-3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA.
3.4
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions Model
Human Body
Description
Series resistance Storage capacitance Number of pulses per pin Series resistance
Symbol
R1 C -- R1 C -- -- --
Value
1500 100 3 0 200 3 -2.5 7.5
Unit
pF -- pF -- V V
Machine
Storage capacitance Number of pulses per pin Minimum input voltage limit
Latch-up Maximum input voltage limit
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 9
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics No.
1 2 3 4
1
Rating1
Human body model (HBM) Machine model (MM) Charge device model (CDM) Latch-up current at TA = 85C Latch-up current at TA = 85C
Symbol
VHBM VMM VCDM ILAT ILAT
Min
2000 200 500 1002 753
Max
-- -- -- -- --
Unit
V V V mA mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 2 These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of 100 mA. 3 This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to 75 mA.
3.5
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes.
Table 7. DC Characteristics (Temperature Range = -40 to 85C Ambient)
Num 1 2 3 4 5 6 7 8 9 10 11 12 C P D P C P P P P C P P C Parameter Supply voltage (run, wait and stop modes) 0 < fBus <10 MHz Minimum RAM retention supply voltage applied to VDD Low-voltage Detection threshold (VDD falling) Power on RESET (POR) voltage Input high voltage (VDD > 5V) (all digital inputs) Input high voltage (2.7 V VDD 5 V) (all digital inputs) Input low voltage (VDD > 5 V) (all digital inputs) Input low voltage (2.7 V VDD 5 V) (all digital inputs) Input hysteresis (all digital inputs) Input leakage current (per pin) VIn = VDD or VSS, all input only pins High impedance (off-state) leakage current (per pin) VIn = VDD or VSS, all input/output Internal pullup/pulldown resistors2(all port pins) Output high voltage (all IOH = -5 mA (VDD 4.5 V) IOH = -3 mA (VDD 3 V) 14 C Maximum total IOH for all port pins |IOHT| -- -- 100 mA ports)3,4 VOH VDD - 0.8 -- -- V Symbol VDD VRAM VLVD VPOR VIH VIH VIL VIL Vhys |IIn| |IOZ| RPU Min 2.7 0.81 Typical -- -- Max 5.5 -- Unit V V V V V V V V V A A k
-- 0.9 0.70 x VDD 0.85 x VDD -- -- 0.06 x VDD -- -- 20
1.8 1.4 -- -- -- -- -- 0.025 0.025 45
-- 1.7 -- -- 0.30 x VDD 0.30 x VDD -- 1.0 1.0 65
13
P
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 10 Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (Temperature Range = -40 to 85C Ambient) (continued)
Num C Parameter Output low voltage (port A)4 IOL = 5 mA (VDD 4.5 V) IOL = 3 mA (VDD 3 V) 16 17 18
1 2 3 4 5 6 7
Symbol
Min
Typical
Max
Unit
15
P
VOL IOLT
--
--
0.8 0.8 100
V
C C C
Maximum total IOL for all port pins dc injection current VIn < VSS, VIn > VDD Single pin limit Total MCU limit, includes sum of all stressed pins Input capacitance (all non-supply pins)
5,6,7
--
--
mA
-- -- CIn --
-- -- --
0.2 0.8 7
mA mA pF
This parameter is characterized and not tested on each device. Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown. The IOH is for high output drive strength. It is tested under high output drive strength only. All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP which is internally clamped to VSS only Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. This parameter is characterized and not tested on each device.
Typical IOH vs. VDD-VOH VDD = 5.5 V
800 700 600 500
mV
400 300 200 100 0 3mA 6mA 9mA 12mA 15mA
-40C 25C 85C
Figure 3. Typical IOH vs. VDD-VOH (VDD = 5.5 V)
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 11
Electrical Characteristics
Typical IOH vs. V DD-V OH V DD = 3.3 V
1800 1600 1400 1200 mV 1000 800 600 400 200 0 3mA 6mA 9mA 12mA 15mA -40C 25C 85C
Figure 4. Typical IOH vs. VDD-VOH (VDD = 3.3 V)
Typical IOL vs. V OL V DD = 5.5 V
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3mA 6mA 9mA 12mA 15mA V
-40C 25C 85C
Figure 5. Typical IOL vs. VOL (VDD = 5.5 V)
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 12 Freescale Semiconductor
Electrical Characteristics
Typical IOL vs. VOL VDD = 3.3 V
1.4 1.2 1 0.8 V 0.6 0.4 0.2 0 3mA 6mA 9mA 12mA 15mA -40C 25C 85C
Figure 6. Typical IOL vs. VOL (VDD = 3.3 V)
VIH vs VDD
3.5 3 2.5 2
V
1.5 1 0.5 0 2.8V 3.0V 3.3V 4.5V 5.0V 5.5V
-40C 25C 85C
Figure 7. Typical VDD vs. VIH
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 13
Electrical Characteristics
VIL vs VDD
2.5
2
1.5 V
1
-40C 25C 85C
0.5
0 2.8V 3.0V 3.3V 4.5V 5.0V 5.5V
Figure 8. Typical VDD vs. VIL
3.6
Num
Supply Current Characteristics
Table 8. Supply Current Characteristics
C Parameter current2 measured Symbol VDD (V) 5 1 P Run supply (fBus = 10 MHz) at RIDD10 3.3 3 2.7 5 2 P Wait mode supply current WIDD1 3.3 3 2.7 5 3 P Stop mode supply current SIDD 3.3 3 2.7 5 4 C ADC adder from stop3 -- 3.3 3 2.7 5 C ACMP adder from stop (ACME = 1) -- 5 3 Typical1 3.71 3.68 3.67 3.66 1.37 1.37 1.37 1.36 1.40 1.35 1.31 1.25 125.45 122.04 121.59 121.22 21 18.5 Unit mA mA mA mA mA mA mA mA A A A A A A A A A A
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 14 Freescale Semiconductor
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num 6 8
1 2
C C C
Parameter RTI adder from stop with 1 kHz clock source enabled4 LVI adder from stop (LVDE = 1 and LVDSE = 1)
Symbol -- --
VDD (V) 5 3 5 3
Typical1 2.4 1.9 70 65
Unit A A A A
Typicals are measured at 25 C. Does not include any dc loads on port pins 3 Required asynchronous ADC clock and LVD to be enabled. 4 Most customers are expected to find that auto-wakeup from stop can be used instead of the higher current wait mode. Wait mode typical is 1.37 mA at 5 V and 3 V with fBus = 10 MHz.
3.7
External (XOSC) and Internal (ICS) Oscillator Characteristics
Reference Figure 9 for crystal or resonator circuit.
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 15
Electrical Characteristics
Table 9. External Oscillator Specifications (Temperature Range = -40 to 85C Ambient)
Characteristic Oscillator crystal or resonator (EREFS = 1) Low range, (IREFS = x) High range, FLL bypassed external (CLKS = 10, IREFS = x) High range, FLL engaged external (CLKS = 00, IREFS = 0) Load capacitors Feedback resistor Low range (32 kHz to 100 kHz) High range (1 MHz to 16 MHz) Series resistor Low range Low Gain (HGO = 0) High Gain (HGO = 1) High range Low Gain (HGO = 0) High Gain (HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time 3, 4 Low range High range Square wave input clock frequency (EREFS = 0) FLL bypass external (CLKS = 10) FLL engaged external (CLKS = 00) Average internal reference frequency - untrimmed Average internal reference frequency - trimmed DCO output frequency range - untrimmed DCO output frequency range - trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature Total deviation of trimmed DCO output frequency over voltage and temperature FLL acquisition time 3,5 Long term Jitter 6 of DCO output clock (averaged over 2ms interval)
1 2
Symbol flo fhi_byp fhi_eng C1 C2 RF
Min 32 1 1
Typical1 -- -- --
Max 38.4 10 10
Unit kHz MHz MHz
See Note 2
10 1
M M
-- -- RS -- -- -- --
t CSTL t CSTH
0 100 0 0 10 20 500 4 -- -- 31.25 31.25 16 16 -- -- -- --
-- -- -- -- -- -- -- -- 20 5 41.66 39.0625 21.33 20 0.2 2 1 0.6 k
-- -- 0 0.03125 25 31.25 12.8 16 -- -- -- --
ms
fextal fint_ut fint_t fdco_ut fdco_t fdco_res_t fdco_t tacquire CJitter
MHz kHz kHz MHz MHz %fdco %fdco ms %fdco
Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. See crystal or resonator manufacturer's recommendation. 3 This parameter is characterized and not tested on each device. 4 Proper PC board layout procedures must be followed to achieve specifications. 5 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 16 Freescale Semiconductor
Electrical Characteristics
6
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
XOSC EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 9. Typical Crystal or Resonator Circuit
3.8
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.8.1
Control Timing
Table 10. Control Timing
Parameter Symbol fBus tRTI textrst tKBIPW tKBIPWS tRise, tFall Min 0 700 150 1.5 tcyc 100 -- -- Typical -- 1000 -- -- -- 11 35 Max 10 1300 -- -- -- -- -- Unit MHz s ns ns ns ns
Bus frequency (tcyc = 1/fBus) Real time interrupt internal oscillator period External RESET pulse width1 KBI pulse width2 KBI pulse width in stop1 Port rise and fall time (load = 50 pF)3 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
1
This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be recognized. 2 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 3 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range -40C to 85C.
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 17
Electrical Characteristics
textrst RESET
Figure 10. Reset Timing
tKBIPWS tKBIPW KBI Pin (rising or high level)
KBI Pin (falling or low level) tKBIPW tKBIPWS
Figure 11. KBI Pulse Width
3.8.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 11. TPM/MTIM Input Timing
Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl fICPW
tTCLK tclkh
Min 0 4 1.5 1.5 1.5
Max fBus1/4 -- -- -- --
Unit MHz tCYC tCYC tCYC tCYC
TCLK tclkl
Figure 12. Timer External Clock
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 18 Freescale Semiconductor
Electrical Characteristics
tICPW TPMCHn
TPMCHn tICPW
Figure 13. Timer Input Capture Pulse
3.9
Analog Comparator (ACMP) Electrical
Table 12. Analog Comparator Electrical Specifications
Characteristic Symbol VDD IDDAC VAIN VAIO VH RAS IALKG tAINIT VBG Min 2.7 -- VSS - 0.3 -- 3.0 -- -- -- 1.208 Typical -- 20 -- 20 9.0 -- -- -- 1.208 Max 5.5 35 VDD 40 15.0 10 1.0 1.0 1.208 Unit V A V mV mV k A s V
Supply voltage Supply current (active) Analog input voltage Analog input offset voltage1 Analog Comparator hysteresis1 Analog source impedance Analog input leakage current Analog Comparator initialization delay Analog Comparator bandgap reference voltage
1
These data are characterized but not production tested. Measurements are made with the device entered STOP mode.
3.10
Internal Clock Source Characteristics
Table 13. Internal Clock Source Specifications
Characteristic Symbol fint_ut fint_t fdco_ut fdco_t fdco_res_t fdco_t tacquire Min 25 31.25 12.8 16 -- -- -- Typical1 31.25 39.06252 16 203 -- -- -- Max 41.66 39.0625 21.33 20 0.2 2 1 Unit kHz kHz MHz MHz %fdco %fdco ms
Average internal reference frequency -- untrimmed Average internal reference frequency -- trimmed DCO output frequency range -- untrimmed DCO output frequency range -- trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature Total deviation of trimmed DCO output frequency over voltage and temperature FLL acquisition time4,5 Stop recovery time (FLL wakeup to previous acquired frequency) IREFSTEN = 0 IREFSTEN = 1
1 2
twakeup
--
100 86
--
s
Data in typical column was characterized at 3.0 V and 5.0 V, 25 C or is typical recommended value. This value has been trimmed to 39.0625 kHz when out of factory 3 This value has been trimmed to 20 MHz when out of factory
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 19
Electrical Characteristics
4 5
This parameter is characterized and not tested on each device. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
3.11
ADC Characteristics
Table 14. 5 Volt 10-bit ADC Operating Conditions
Characteristic Conditions Absolute Symbol VDDAD VDDAD VSSAD VREFH VREFL VADIN CADIN RADIN Min 2.7 -100 -100 2.7 VSSAD VREFL -- -- -- -- -- 0.4 fADCK 0.4 Typical1 -- 0 0 VDDAD VSSAD -- 4.5 3 -- -- -- -- -- Max 5.5 100 100 VDDAD VSSAD VREFH 5.5 5 5 10 10 8.0 MHz 4.0 Unit V mV mV V V V pF k
Supply voltage Ground voltage Ref voltage high Ref voltage low Input voltage Input capacitance Input resistance
Delta to VDD (VDD - VDDAD)2 Delta to VSS (VSS - VSSAD)2 -- -- -- -- -- 10-bit mode fADCK > 4MHz fADCK < 4MHz 8-bit mode (all valid fADCK)
Analog source resistance external to MCU
RAS
k
ADC conversion clock frequency
1
High speed (ADLPC = 0) Low power (ADLPC = 1)
Typical values assume VDDAD = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 20 Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ -
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 14. ADC Input Impedance Equivalency Diagram Table 15. 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic Supply current ADLPC=1 ADLSMP=1 ADCO=1 Supply current ADLPC=1 ADLSMP=0 ADCO=1 Supply current ADLPC=0 ADLSMP=1 ADCO=1 Supply current ADLPC=0 ADLSMP=0 ADCO=1 Supply current ADC asynchronous clock source Conditions C Symbol Min Typical1 Max Unit
T
IDDAD
--
133
--
A
T
IDDAD
--
218
--
A
T
IDDAD
--
327
--
A
VDDAD 5.5 V
P
IDDAD
--
0.582
1
mA
Stop, Reset, Module Off High Speed (ADLPC = 0) P Low Power (ADLPC = 1)
IDDAD fADACK
-- 2 1.25
0.011 3.3 2
1 5
A MHz
3.3
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 21
Electrical Characteristics
Table 15. 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic Conversion time (Including sample time) Conditions Short Sample (ADLSMP = 0) Long Sample (ADLSMP = 1) Short Sample (ADLSMP = 0) Long Sample (ADLSMP = 1) 10-bit mode Total unadjusted error 8-bit mode 10-bit mode P Differential non-linearity 8-bit mode DNL -- P ETUE C Symbol Min -- P tADC -- -- P tADS -- -- -- -- 23.5 1 0.5 0.5 0.3 -- 2.5 1.0 1.0 0.5 LSB2 40 3.5 -- -- ADCK cycles Typical1 20 Max -- Unit ADCK cycles
Sample time
LSB2
Monotonicity and no-missing-code guaranteed 10-bit mode Integral non-linearity 8-bit mode 10-bit mode Zero-scale error 8-bit mode Full-scale error VADIN = VDDA Quantization error 8-bit mode Input leakage error pad leakage3 * RAS
1
-- C INL -- -- P EZS -- -- P EFS -- -- D EQ -- -- D EIL --
0.5 0.3 0.5 0.5 0.5 0.5 -- -- 0.2 0.1
1.0 0.5 1.5 0.5 1.5 0.5 0.5 0.5 2.5 1
LSB2
LSB2
10-bit mode 8-bit mode 10-bit mode
LSB2
LSB2
10-bit mode 8-bit mode
LSB2
Typical values assume VDDAD = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Based on input pad leakage current. Refer to pad electrical.
3.12
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.12.1
Control Timing
Table 16. Control Timing
Characteristic Symbol fBus tRTI Min DC 700 Typical -- 1000 Max 10 1300 Unit MHz s
Bus frequency (tcyc = 1/fBus) Real time interrupt internal oscillator period
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 22 Freescale Semiconductor
Electrical Characteristics
Table 16. Control Timing (continued)
Characteristic External RESET pulse width1 KBI pulse width2 KBI pulse width in stop1 Port rise and fall time (load = 50 pF)3 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
1
Symbol textrst tKBIPW tKBIPWS tRise, tFall
Min 150 1.5 tcyc 100 -- --
Typical
Max -- -- --
Unit ns ns ns ns
11 35
-- --
This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be recognized. 2 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 3 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 C to 85 C.
textrst RESET
Figure 15. Reset Timing
tKBIPWS tKBIPW KBI Pin (rising or high level)
KBI Pin (falling or low level) tKBIPW tKBIPWS
Figure 16. KBI Pulse Width
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. For detailed information about program/erase operations, see the reference manual.
Table 17. Flash Characteristics
Characteristic Supply voltage for program/erase Program/Erase voltage VPP current Program Mass erase Supply voltage for read operation 0 < fBus < 10 MHz IVPP_prog IVPP_erase VRead -- -- 2.7 -- -- -- 200 100 5.5 A A V Symbol VDD VPP Min 2.7 11.8 Typical1 -- 12 Max 5.5 12.2 Unit V V
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 23
Electrical Characteristics
Table 17. Flash Characteristics (continued)
Characteristic Byte program time Mass erase time Cumulative program HV time2 Total cumulative HV time (total of tme & thv applied to device) HVEN to program setup time PGM/MASS to HVEN setup time HVEN hold time for PGM HVEN hold time for MASS VPP to PGM/MASS setup time HVEN to VPP hold time VPP rise time3 Recovery time Program/erase endurance TL to TH = -40 C to 85 C Data retention
1 2
Symbol tprog tme thv thv_total tpgs tnvs tnvh tnvh1 tvps tvph tvrs trcv -- tD_ret
Min 20 500 -- -- 10 5 5 100 20 20 200 1 1000 15
Typical1 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max 40 -- 8 2 -- -- -- -- -- -- -- -- -- --
Unit s ms ms hours s s s s ns ns ns s cycles years
Typicals are measured at 25 C. thv is the cumulative high voltage programming time to the same row before next erase. Same address can not be programmed more than twice before next erase. 3 Fast V PP rise time may potentially trigger the ESD protection structure, which may result in over current flowing into the pad and cause permanent damage to the pad. External filtering for the VPP power source is recommended. An example VPP filter is shown in Figure 17.
100 VPP 12 V 1 nF
Figure 17. Example VPP Filtering
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 24 Freescale Semiconductor
Ordering Information
tprog WRITE DATA1 tpgs
Data Next Data
PGM tnvs HVEN trs VPP2 tnvh trcv
tvps thv
tvph
1
Next Data applies if programming multiple bytes in a single row, refer to MC9RS08LA8 Series Reference Manual. 2V DD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 18. Flash Program Timing
tme trcv MASS tnvs HVEN trs VPP1
1
tnvh1
tvps
tvph
VDD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 19. Flash Mass Erase Timing
4
Ordering Information
This section contains ordering numbers for MC9RS08LA8 devices. See below for an example of the device numbering system.
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 Freescale Semiconductor 25
Mechanical Drawings
Table 18. Device Numbering System
Memory Device Number FLASH MC9RS08LA8 8 KB RAM 256 bytes Type 48-Pin QFN 48-Pin LQFP Designator FT LF Document No. 98ARH99048A 98ASH00962A Package
MC 9 RS08 LA 8 C XX Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family Package designator (See Table 18) Temperature range (C = -40C to 85C) Approximate memory size (in KB)
5
Mechanical Drawings
This following pages contain mechanical specifications for MC9RS08LA8 series package options. * 48-pin QFN (quad flat non-leader) * 48-pin LQFP (low-profile quad flat-pack)
MC9RS08LA8 Series MCU Data Sheet, Rev. 1 26 Freescale Semiconductor
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Document Number: MC9RS08LA8 Rev. 1 10/2008

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